1. Field of the Invention
The present invention relates to an overvoltage protection circuit which protects an internal circuit of a semiconductor integrated circuit from abnormal overvoltage.
2. Description of the Related Art
Semiconductor integrated circuits contain internal circuits such as an inverter circuit, a buffer circuit, and various passive elements, and has incorporated therein a surge protection circuit for protecting such internal circuits from abnormal overvoltage. For example, in the process of manufacturing or testing of electronic instruments, electrostatic discharge (ESD) can occur due to static electricity produced by friction or electrification, and thereby an excessively large abnormal voltage (surge voltage) can instantaneously be input through an external terminal of a semiconductor chip. The surge protection circuit operates in response to the abnormal voltage, and protects destruction and maloperation of the internal circuit, by allowing overcurrent (surge current) produced by the abnormal voltage to be drawn into a GND interconnect. Typical circuits of such surge protection circuits are disclosed in Japanese Patent Application Publication Nos. 2009-111337 and 2007-59543.
FIG. 1 schematically illustrates an exemplary conventional surge protection circuit 100. As illustrated in FIG. 1, the surge protection circuit 100 has a plurality of n-channel MOS transistors N01, N02, . . . , N0n−1, N0n connected in parallel, between an input terminal 101 and a VSS terminal 102. Each of the MOS transistors has a source, a gate, a back gate connected to the VSS terminal 102, and a drain connected to the input terminal 101. Also an internal circuit 90 is connected to the input terminal 101.
When an excessively large abnormal voltage is input through the input terminal 101, each of the MOS transistors N01 to N0n starts to respond to the surge voltage, upon being triggered by breakdown of a parasitic diode configured by the drain and the back gate. In each of the MOS transistors N01 to N0n, the parasitic bipolar transistor (npn-type bipolar transistor) turns on in response to current running into the base (substrate) of the parasitic bipolar transistor, and current flows to the emitter. As a consequence, the MOS transistors N01 to N0n draw the surge current into the VSS terminal 102. Accordingly, the internal circuit 90 can be protected from the surge voltage, if the MOS transistors N01 to N0n successfully draw the surge current into the VSS terminal 102, before the internal circuit 90 responds to the surge voltage.
The conventional surge protection circuit 100 has, however, been suffering from a problem that it may fail in predominantly draw the surge current into the VSS terminal 102, and that the internal circuit 90 may therefore be destructed in response to the surge voltage, due to variation in the time of causing breakdown of the plurality of MOS transistors N01 to N0n.
In view of the foregoing, it is an object of the present invention to provide an overvoltage protection circuit which can surely protect the internal circuit from abnormal overvoltage, and to provide a semiconductor integrated circuit having the same.